In the manufacture of integrated circuits, a commonly used practice is to form silicide on source/drain regions and on polysilicon gates. This practice has become increasingly important for very high density devices where the feature size is reduced to a fraction of a micrometer. Silicide provides good ohmic contact, reduces the sheet resistivity of source/drain regions and polysilicon gates, increases the effective contact area, and provides an etch stop. A common technique employed in the semiconductor manufacturing industry is the self-aligned silicide ("salicide") processing period. Salicide processing involves the deposition of a metal that forms intermetallic with silicon (Si), but does not react with silicon oxide or silicon nitride. Common metals employed in salicide processing are titanium (Ti), cobalt (Co), and nickel (Ni). These common metals form low resistivity phases with silicon, such as TiSi.sub.2, CoSi.sub.2, NiSi. The metal is deposited with a uniform thickness across the entire semiconductor wafer. This is accomplished using, for example, physical vapor deposition (PVD) from an ultra-pure sputtering target and a commercially available ultra-high vacuum (UHV), multi-chamber, DC magnetron sputtering system. Deposition is performed after both gate etch and source/drain junction formation. After deposition, the metal blankets the polysilicon gate electrode, the oxide spacers, the oxide isolation, and the exposed source and drain electrodes. A cross section of an exemplary semiconductor wafer during one stage of a salicide formation process in accordance with the prior art techniques is depicted in FIG. 1.
As shown in FIG. 1, a silicon substrate 10 has been provided with the source/drain junctions 12, 14 and a polysilicon gate 16. Oxide spacers 18 have been formed on the sides of the polysilicon gate 16. The refractory metal layer 20 has been blanket deposited over the source/drain junctions 12, 14, the polysilicon gate 16 and the spacers 18. The metal layer 20 also blankets oxide isolation regions 22 that isolate the devices from one another.
A first rapid thermal anneal (RTA) step is then performed at a temperature of between 450.degree.-700.degree. C. for a short period of time in a nitrogen atmosphere. The nitrogen reacts to form a metal nitride at the surface of the metal, while the metal reacts with silicon and forms silicide in those regions where it comes in direct contact with the silicon. Hence, the reaction of the metal with the silicon forms a silicide 24 on the gate 16 and source/drain regions 12, 14, as depicted in FIG. 2. After the first rapid thermal anneal step, any metal that is unreacted is stripped away using a wet etch process that is selective to the silicide. The second, higher temperature rapid thermal anneal step, for example above 700.degree. C., is applied to form a lower resistance silicide phase of the metal silicide. The resulting structure is depicted in FIG. 3 in which the higher resistivity metal silicide 24 has been transformed to the lowest resistivity phase metal silicide 26. For example, when the metal is cobalt, the higher resistivity phase is CoSi and the lowest resistivity phase is CoSi.sub.2. When the polysilicon and diffusion patterns are both exposed to the metal, the silicide forms simultaneously over both regions so that this method is described as "salicide" since the silicides formed over the polysilicon and single-crystal silicon are self-aligned to each other.
Titanium is currently the most prevalent metal used in the integrated circuit industry, largely because titanium is already employed in other areas such as 0.5 micron CMOS logic technologies. In the first rapid thermal anneal step, the so-called "C49" crystallographic titanium phase is formed, and the lower resistance "C54" phase forms during the second rapid thermal anneal step. However, the titanium silicide sheet resistance rises dramatically due to narrow-line effects. This is described in European publication number 0651076. Cobalt silicide (CoSi.sub.2) has therefore been introduced by several integrated circuit manufacturers as the replacement for titanium silicide. Since cobalt silicide forms by a diffusion reaction, it does not display the narrow-line effects observed with titanium silicide that forms by nucleation-and-growth. Some of the other advantages of cobalt over alternative materials such as titanium, platinum, or palladium are that cobalt silicide provides low resistivity, allows lower-temperature processing, and has a reduced tendency for forming diode-like interfaces.
One of the concerns associated with cobalt silicide technologies is that of junction leakage, which occurs when cobalt silicide is formed such that it extends to the bottom and beyond of the source and drain junctions. An example of this occurrence is depicted in FIG. 3. A source of this problem is the high silicon consumption during the salicide formation process. One way to account for the high consumption of silicon during salicide processing is to make the junctions deeper. Making the junctions deeper, however, is counter to the desire for extremely shallow source and drain junctions that support device scaling, and negatively impacts device performance.